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Low Cost, Low Power 12-Bit Differential ADC Driver AD8137
FEATURES
Fully differential Extremely low power with power-down feature 2.6 mA quiescent supply current @ 5 V 450 A in power-down mode @ 5 V High speed 110 MHz large signal 3 dB bandwidth @ G = 1 450 V/s slew rate 12-bit SFDR performance @ 500 kHz Fast settling time: 100 ns to 0.02% Low input offset voltage: 2.6 mV max Low input offset current: 0.45 A max Differential input and output Differential-to-differential or single-ended-to-differential operation Rail-to-rail output Adjustable output common-mode voltage Externally adjustable gain Wide supply voltage range: 2.7 V to 12 V Available in small SOIC package
FUNCTIONAL BLOCK DIAGRAM
AD8137
-IN 1 VOCM 2 VS+ 3 +OUT 4
8 7 6 5
+IN PD
04771-0-001
VS- -OUT
Figure 1.
3 2 G=1
NORMALIZED CLOSED-LOOP GAIN (dB)
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 RG = 1k VO, dm = 0.1V p-p -11 -12 0.1 1
04771-0-002
G=5
G=2
G = 10
APPLICATIONS
12-bit ADC drivers Portable instrumentation Battery-powered applications Single-ended-to-differential converters Differential active filters Video amplifiers Level shifters
10 FREQUENCY (MHz)
100
1000
Figure 2. Small Signal Response for Various Gains
GENERAL DESCRIPTON
The AD8137 is a low cost differential driver with a rail-to-rail output that is ideal for driving 12-bit ADCs in systems that are sensitive to power and cost. The AD8137 is easy to apply, and its internal common-mode feedback architecture allows its output common-mode voltage to be controlled by the voltage applied to one pin. The internal feedback loop also provides inherently balanced outputs as well as suppression of even-order harmonic distortion products. Fully differential and single-ended-todifferential gain configurations are easily realized by the AD8137. External feedback networks consisting of four resistors determine the amplifier's closed-loop gain. The power-down feature is beneficial in critical low power applications. The AD8137 is manufactured on Analog Devices' proprietary second generation XFCB process, enabling it to achieve high levels of performance with very low power consumption. The AD8137 is available in the small 8-lead SOIC package and 3 mm x 3 mm LFCSP. It is rated to operate over the extended industrial temperature range of -40C to +125C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
AD8137 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 17 Applications..................................................................................... 18 Analyzing a Typical Application with Matched RF and RG Networks...................................................................................... 18 Estimating Noise, Gain, and Bandwith with Matched Feedback Networks .................................................................... 18 Driving an ADC with Greater than 12-Bit Performance...... 22 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
7/05--Rev. A to Rev. B Changes to Ordering Guide .......................................................... 24 8/04--Rev. 0 to Rev. A. Added 8-Lead LFCSP.........................................................Universal Changes to Layout ..............................................................Universal Changes to Product Title ................................................................. 1 Changes to Figure 1.......................................................................... 1 Changes to Specifications ................................................................ 3 Changes to Absolute Maximum Ratings ....................................... 6 Changes to Figure 4 and Figure 5................................................... 7 Added Figure 6, Figure 20, Figure 23, Figure 35, Figure 48, and Figure 58; Renumbered Successive Figures ........................... 7 Changes to Figure 32...................................................................... 12 Changes to Figure 40...................................................................... 13 Changes to Figure 55...................................................................... 16 Changes to Table 7 and Figure 63................................................. 18 Changes to Equation 19 ................................................................. 19 Changes to Figure 64 and Figure 65............................................. 20 Changes to Figure 66...................................................................... 22 Added Driving an ADC with Greater Than 12-Bit Performance Section ...................................................................... 22 Changes to Ordering Guide .......................................................... 24 Updated Outline Dimensions ....................................................... 24 5/04--Revision 0: Initial Version
Rev. B | Page 2 of 24
AD8137 SPECIFICATIONS
VS = 5 V, VOCM = 0 V (@ 25C, differential gain = 1, RL, dm = RF = RG = 1 k, unless otherwise noted, TMIN to TMAX = -40C to +125C). Table 1.
Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Slew Rate Settling Time to 0.02% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE SFDR Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error VOCM to VO, cm PERFORMANCE VOCM DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Gain VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Input Bias Current CMRR POWER SUPPLY Operating Range Quiescent Current Quiescent Current, Disabled PSRR PD PIN Threshold Voltage Input Current OPERATING TEMPERATURE RANGE Conditions Min Typ Max Unit
VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 2 V step VO, dm = 3.5 V step G = 2, VI, dm = 12 V p-p triangle wave VO, dm = 2 V p-p, fC = 500 kHz VO, dm = 2 V p-p, fC = 2 MHz f = 50 kHz to 1 MHz f = 50 kHz to 1 MHz VIP = VIN = VOCM = 0 V TMIN to TMAX TMIN to TMAX
64 79
76 110 450 100 85 90 76 8.25 1
MHz MHz V/s ns ns dB dB nV/Hz pA/Hz +2.6 1 0.45 mV V/C A A dB V K K pF dB V mA dB
-2.6
0.7 3 0.5 0.1 91
-4 Differential Common-mode Common-mode VICM = 1 V Each single-ended output, RL, dm = 1 k f = 1 MHz 800 400 1.8 79
+4
66 VS- + 0.55
VS+ - 0.55 20 -64
VO, cm = 0.1 V p-p VO, cm = 0.5 V p-p 0.992 -4 -28 f = 100 kHz to 1 MHz VO, dm/VOCM, VOCM = 0.5 V 62 +2.7 Power-down = low VS = 1 V
58 63 1.000
1.008 +4
MHz V/s V/V V k mV nV/Hz A dB V mA A dB V A C
35 11 18 0.3 75
+28 1.1
79 VS- + 0.7
3.2 750 91
6 3.6 900
Power-Down = high/low -40
150/210
VS- + 1.7 170/240 +125
Rev. B | Page 3 of 24
AD8137
VS = 5 V, VOCM = 2.5 V (@ 25C, differential gain = 1, RL, dm = RF = RG = 1 k, unless otherwise noted, TMIN to TMAX = -40C to +125C). Table 2.
Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Slew Rate Settling Time to 0.02% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE SFDR Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error VOCM to VO, cm PERFORMANCE VOCM DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Gain VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Input Bias Current CMRR POWER SUPPLY Operating Range Quiescent Current Quiescent Current, Disabled PSRR PD PIN Threshold Voltage Input Current OPERATING TEMPERATURE RANGE Conditions Min Typ Max Unit
VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 2 V step VO, dm = 3.5 V step G = 2, VI, dm = 7 V p-p triangle wave VO, dm = 2 V p-p, fC = 500 kHz VO, dm = 2 V p-p, fC = 2 MHz f = 50 kHz to 1 MHz f = 50 kHz to 1 MHz VIP = VIN = VOCM = 0 V TMIN to TMAX TMIN to TMAX
63 76
75 107 375 110 90 89 73 8.25 1
MHz MHz V/s ns ns dB dB nV/Hz pA/Hz +2.7 0.9 0.45 mV V/C A A dB V K K pF dB V mA dB
-2.7
0.7 3 0.5 0.1 89
1 Differential Common-mode Common-mode VICM = 1 V Each single-ended output, RL, dm = 1 k f = 1 MHz 800 400 1.8 90
4
64 VS- + 0.45
VS+ - 0.45 20 -64
VO, cm = 0.1 V p-p VO, cm = 0.5 V p-p 0.980 1 -25 f = 100 kHz to 5 MHz VO, dm /VOCM, VOCM = 0.5 V 62 +2.7 Power-down = low VS = 1 V
60 61 1.000
1.020 4
MHz V/s V/V V k mV nV/Hz A dB V mA A dB V A C
35 7.5 18 0.25 75
+25 0.9
79 VS- + 0.7
2.6 450 91
6 2.8 600
Power-down = high/low -40
50/110
VS- + 1.5 60/120 +125
Rev. B | Page 4 of 24
AD8137
VS = 3 V, VOCM = 1.5 V (@ 25C, differential gain = 1, RL, dm = RF = RG = 1 k, unless otherwise noted, TMIN to TMAX = -40C to +125C). Table 3.
Parameter DIFFERENTIAL INPUT PERFORMANCE DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth -3 dB Large Signal Bandwidth Slew Rate Settling Time to 0.02% Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE SFDR Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Common-Mode Voltage Range Input Resistance Input Capacitance CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error VOCM to VO, cm PERFORMANCE VOCM DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Gain VOCM INPUT CHARACTERISTICS Input Voltage Range Input Resistance Input Offset Voltage Input Voltage Noise Input Bias Current CMRR POWER SUPPLY Operating Range Quiescent Current Quiescent Current, Disabled PSRR PD PIN Threshold Voltage Input Current OPERATING TEMPERATURE RANGE Conditions Min Typ Max Unit
VO, dm = 0.1 V p-p VO, dm = 2 V p-p VO, dm = 2 V Step VO, dm = 3.5 V Step G = 2, VI, dm = 5 V p-p Triangle Wave VO, dm = 2 V p-p, fC = 500 kHz VO, dm = 2 V p-p, fC = 2 MHz f = 50 kHz to 1 MHz f = 50 kHz to 1 MHz VIP = VIN = VOCM = 0 V TMIN to TMAX TMIN to TMAX
61 62
73 93 340 110 100 89 71 8.25 1
MHz MHz V/s ns ns dB dB nV/Hz pA/Hz +2.75 0.9 0.4 mV V/C A A dB V M M pF dB V mA dB
-2.75
0.7 3 0.5 0.1 87
1 Differential Common-mode Common-mode VICM = 1 V Each single-ended output, RL, dm = 1 k f = 1 MHz 800 400 1.8 80
2
64 VS- + 0.37
VS+ - 0.37 20 -64
VO, cm = 0.1 V p-p VO, cm = 0.5 V p-p 0.96 1.0 -25 f = 100 kHz to 5 MHz VO, dm /VOCM, VOCM = 0.5 V 62 +2.7 Power-down = low VS = 1 V
61 59 1.00
1.04 2.0
MHz V/s V/V V k mV nV/Hz A dB V mA A dB V A C
35 5.5 18 0.3 74
+25 0.7
78 VS- + 0.7
2.3 345 90
6 2.5 460
Power-down = high/low -40
8/65
VS- + 1.5 10/70 +125
Rev. B | Page 5 of 24
AD8137 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage VOCM Power Dissipation Input Common-Mode Voltage Storage Temperature Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature Rating 12 V VS+ to VS- See Figure 3 VS+ to VS- -65C to +125C -40C to +125C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The load current consists of differential and common-mode currents flowing to the load, as well as currents flowing through the external feedback networks and the internal common-mode feedback loop. The internal resistor tap used in the common-mode feedback loop places a 1 k differential load on the output. RMS output voltages should be considered when dealing with ac signals. Airflow reduces JA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the SOIC-8 (125C/W) and LFCSP (JA = 70C/W) package on a JEDEC standard 4-layer board. JA values are approximations.
3.0
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for the device soldered in a circuit board in still air. Table 5. Thermal Resistance
Package Type SOIC-8/2-Layer SOIC-8/4-Layer LFCSP/4-Layer JA 157 125 70 JC 56 56 56 Unit C/W C/W C/W
MAXIMUM POWER DISSIPATION (W)
2.5 LFCSP
2.0
1.5
Maximum Power Dissipation
The maximum safe power dissipation in the AD8137 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8137. Exceeding a junction temperature of 175C for an extended period of time can result in changes in the silicon devices, potentially causing failure.
1.0 SOIC-8 0.5
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 6 of 24
04771-0-022
AD8137 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8137
-IN 1 VOCM 2 VS+ 3 +OUT 4
8 7 6 5
+IN PD
04771-0-001
VS- -OUT
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic -IN VOCM VS+ +OUT -OUT VS- PD +IN Description Inverting Input. An internal feedback loop drives the output common-mode voltage to be equal to the voltage applied to the VOCM pin, provided the amplifier's operation remains linear. Positive Power Supply Voltage. Positive Side of the Differential Output. Negative Side of the Differential Output. Negative Power Supply Voltage. Power Down. Noninverting Input.
RF 50 52.3 VTEST 50 RG = 1k VOCM CF + - RL, dm 1k VO, dm +
04771-0-023
MIDSUPPLY 52.3
AD8137
- CF
TEST SIGNAL SOURCE
RG = 1k
RF
Figure 5. Basic Test Circuit
50 52.3 VTEST 50 RG = 1k VOCM
RF = 1k RS +
- CL, dm RL, dm VO, dm +
04771-0-062
MIDSUPPLY 52.3
AD8137
- RS RF = 1k
TEST SIGNAL SOURCE
RG = 1k
Figure 6. Capacitive Load Test Circuit, G = 1
Rev. B | Page 7 of 24
AD8137 TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, differential gain = 1, RG = RF = RL, dm = 1 k, VS = 5 V, TA = 25C, VOCM = 2.5V. Refer to the basic test circuit in Figure 5 for the definition of terms.
3 2 G=1
3 2
NORMALIZED CLOSED-LOOP GAIN (dB)
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9
04771-0-002
NORMALIZED CLOSED-LOOP GAIN (dB)
G=1
1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 RG = 1k -11 VO, dm = 2.0V p-p -12 0.1 1
04771-0-004
G=5
G=2
G=5
G=2
G = 10
G = 10
-10 -11 -12 0.1
RG = 1k VO, dm = 0.1V p-p 1 10 FREQUENCY (MHz) 100
1000
10 FREQUENCY (MHz)
100
1000
Figure 7. Small Signal Frequency Response for Various Gains
3 2 1 0 VS = +5 VS = +3
Figure 10. Large Signal Frequency Response for Various Gains
4 3 2 1 VS = +5 VS = +3
CLOSED-LOOP GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 -8 -9
CLOSED-LOOP GAIN (dB)
VS = 5
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 1
04771-0-005
VS = 5
-10 -11 -12 1 VO, dm = 0.1V p-p 10 100 FREQUENCY (MHz)
04771-0-003
VO, dm = 2.0V p-p 10 100 FREQUENCY (MHz)
1000
1000
Figure 8. Small Signal Frequency Response for Various Power Supplies
Figure 11. Large Signal Frequency Response for Various Power Supplies
3 2 1 0
4 3 2 1 T = +25C
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 VO, dm = 0.1V p-p
T = +85C T = +25C T = +125C T = -40C
0 -1 -2 -3 -4 -5 -6 -7 -8 T = -40C VO, dm = 2.0V p-p 1 10 100 FREQUENCY (MHz)
04771-0-007
T = +85C
T = +125C
04771-0-006
-9 -10 -11
10 100 FREQUENCY (MHz)
1000
1000
Figure 9. Small Signal Frequency Response at Various Temperatures
Figure 12. Large Signal Frequency Response at Various Temperatures
Rev. B | Page 8 of 24
AD8137
3 2 1 0 RL, dm = 1k RL, dm = 500
3 2 1 0
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
-1 -2 -3 -4 -5 -6 -7 -8 -9
RL, dm = 2k
-1 -2 -3 -4 -5 -6 -7 -8 -9 RL, dm = 500 RL, dm = 1k VO, dm = 2V p-p 1 10 100 FREQUENCY (MHz)
04771-0-043
RL, dm = 2k
-10 -11 -12 1 VO, dm = 0.1V p-p 10 100 FREQUENCY (MHz)
04771-0-041
-10 -11 -12
1000
1000
Figure 13. Small Signal Frequency Response for Various Loads
Figure 16. Large Signal Frequency Response for Various Loads
3 2 1 0
CLOSED-LOOP GAIN (dB)
3 CF = 0pF 2 1 0
CLOSED-LOOP GAIN (dB)
CF = 0pF CF = 1pF
-1 -2 -3 -4 -5 -6 -7 -8 -9 CF = 2pF
CF = 1pF
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 1 VO, dm = 2.0V p-p 10 100 FREQUENCY (MHz)
04771-0-009
CF = 2pF
-10 -11 -12 1 VO, dm = 0.1V p-p 10 100 FREQUENCY (MHz)
1000
04771-0-008
1000
Figure 14. Small Signal Frequency Response for Various CF
2 1 0 -1
CLOSED-LOOP GAIN (dB)
Figure 17. Large Signal Frequency Response for Various CF
3
VOCM = 4V
VOCM = 2.5V
2 1
CLOSED-LOOP GAIN (dB)
-2 -3 -4 -5 -6 -7 -8 -9 -10
VOCM = 1V
0 -1 -2 -3 -4 -5 -6 -7 -8 -9
04771-0-042
0.5V p-p
2V p-p 1V p-p
04771-0-044
-11 -12 -13 1 VO, dm = 0.1V p-p 10 100 FREQUENCY (MHz)
-10 -11 -12 1
0.1V p-p
1000
10 100 FREQUENCY (MHz)
1000
Figure 15. Small Signal Frequency Response at Various VOCM
Figure 18. Frequency Response for Various Output Amplitudes
Rev. B | Page 9 of 24
AD8137
4 3 2 1
4 3 2 1
CLOSED-LOOP GAIN (dB)
RF = 500 RF = 2k RF = 1k
CLOSED-LOOP GAIN (dB)
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 1
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 1 G=1 VO, dm = 2V p-p 10 100 FREQUENCY (MHz)
04771-0-036
RF = 2k RF = 1k
RF = 500
04771-0-037
G=1 VS = 5V VO, dm = 0.1V p-p 10 100 FREQUENCY (MHz)
1000
1000
Figure 19. Small Signal Frequency Response for Various RF
-65 -70 -75
DISTORTION (dBc)
Figure 22. Large Signal Frequency Response for Various RF
-40 G=1 VO, dm = 2V p-p
G=1 VO, dm = 2V p-p
-50
VS = +3V
-80 -85 -90 -95 -100 -105 0.1
04771-0-045
DISTORTION (dBc)
-60 VS = +3V VS = +5V
VS = +5V VS = 5V
-70 -80
-90 -100 -110 0.1
VS = 5V
04771-0-063
1 FREQUENCY (MHz)
10
1 FREQUENCY (MHz)
10
Figure 20. Second Harmonic Distortion vs. Frequency and Supply Voltage
Figure 23. Third Harmonic Distortion vs. Frequency and Supply Voltage
-50 -55 -60
DISTORTION (dBc) DISTORTION (dBc)
-50 FC = 500kHz SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE -55 -60 VS = +5V -65 -70 -75 -80 VS = +5V -85 VS = +5V
04771-0-027
VS = +3V
-65 VS = +5V -70 -75 -80 -85 -90 -95 -100 0.25 1.25 2.25 3.25 4.25 5.25 6.25 VO, dm (V p-p) 7.25 8.25 VS = +3V VS = +3V
VS = +3V -90 -95 -100 0.25 1.25 2.25 3.25
04771-0-026
FC = 2MHz SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE 4.25 5.25 6.25 VO, dm (V p-p) 7.25 8.25
9.25
9.25
Figure 21. Harmonic Distortion vs. Output Amplitude and Supply, FC = 500 kHz
Figure 24. Harmonic Distortion vs. Output Amplitude and Supply, FC = 2 MHz
Rev. B | Page 10 of 24
AD8137
-40 VO, dm = 2V p-p -50 -50 -40 VO, dm = 2V p-p
DISTORTION (dBc)
DISTORTION (dBc)
-60 -70 RL, dm = 200
-60 -70 RL, dm = 200
-80 -90 RL, dm = 500
RL, dm = 1k
-80 RL, dm = 1k -90 RL, dm = 500
04771-0-032
-110 0.1
1 FREQUENCY (MHz)
10
-110 0.1
1 FREQUENCY (MHz)
10
Figure 25. Second Harmonic Distortion at Various Loads
Figure 28. Third Harmonic Distortion at Various Loads
-40 VO, dm = 2V p-p RG = 1k -50 G=2
DISTORTION (dBc)
-40 VO, dm = 2V p-p RG = 1k -50
G=5 -70 G=1
DISTORTION (dBc)
-60
-60 -70
G=5
G=2 -80 G=1 -90
-80 -90
04771-0-034
-110 0.1
1 FREQUENCY (MHz)
10
-110 0.1
1 FREQUENCY (MHz)
10
Figure 26. Second Harmonic Distortion at Various Gains
Figure 29. Third Harmonic Distortion at Various Gains
-40 VO, dm = 2V p-p G=1 -50
-40 VO, dm = 2V p-p G=1 -50
DISTORTION (dBc)
-70
RF = 500
DISTORTION (dBc)
-60
-60 -70
-80 RF = 2k -90 RF = 1k
04771-0-030
-80 -90
RF = 500
04771-0-031
-100 -110 0.1
-100 -110 0.1 RF = 1k
RF = 2k 1 FREQUENCY (MHz)
1 FREQUENCY (MHz)
10
10
Figure 27. Second Harmonic Distortion at Various RF
Figure 30. Third Harmonic Distortion at Various RF
Rev. B | Page 11 of 24
04771-0-035
-100
-100
04771-0-033
-100
-100
AD8137
-50 FC = 500kHz VO, dm = 2V p-p SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE
-50 FC = 500kHz VO, dm = 2V p-p SECOND HARMONIC SOLID LINE THIRD HARMONIC DASHED LINE
-60
-60
DISTORTION (dBc)
-70
DISTORTION (dBc)
-70
-80
-80
-90
-90
04771-0-028
-110 0.5
1.0
1.5
2.0
2.5 VOCM (V)
3.0
3.5
4.0
4.5
-110 0.5
0.7
0.9
1.1
1.3
1.5 1.7 VOCM (V)
1.9
2.1
2.3
2.5
Figure 31. Harmonic Distortion vs. VOCM, VS = 5 V
Figure 34. Harmonic Distortion vs. VOCM, VS = 3 V
100
1000
INPUT VOLTAGE NOISE (nV/Hz)
VOCM NOISE (nV/Hz)
100
10
10
04771-0-046
1 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100M
1 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100M
Figure 32. Input Voltage Noise vs. Frequency
20 10 0 -10
CMRR (dB)
-30 -10
Figure 35. VOCM Voltage Noise vs. Frequency
VIN, cm = 0.2V p-p INPUT CMRR = VO, cm/VIN, cm
-20
VO, cm = 0.2V p-p VOCM CMRR = VO, dm/VOCM
-20 -30 -40 -50 -60
04771-0-013
VOCM CMRR (dB)
-40
-50 -60
-70 -80 1 10 FREQUENCY (MHz) 100
-70 -80 1 10 FREQUENCY (MHz) 100
Figure 33. CMRR vs. Frequency
Figure 36. VOCM CMRR vs. Frequency
Rev. B | Page 12 of 24
04771-0-012
04771-0-047
04771-0-029
-100
-100
AD8137
8 G=2 6 OUTPUT 4 INPUT x 2
2.0 1.5 1.0 VO, dm INPUT CF = 0pF VO, dm = 3.5V p-p
VOLTAGE (V)
2 0 -2 -4
04771-0-016
0.5 0 ERROR = VO, dm - INPUT -0.5 TSETTLE = 110ns -1.0 -1.5 50ns/DIV -2.0 TIME (ns)
-6 250ns/DIV -8 TIME (ns)
Figure 37. Overdrive Recovery
100 75 50 CF = 0pF CF = 1pF
Figure 40. Settling Time (0.02%)
1.5 CF = 0pF 1.0 CF = 1pF CF = 0pF 0.5 CF = 1pF 0 1V p-p 2V p-p
VO, dm (mV)
0 -25 -50 -75 VO, dm = 100mV p-p -100 TIME (ns) 10ns/DIV
04771-0-015
VO, dm (V)
25
-0.5
20ns/DIV -1.5 TIME (ns)
Figure 38. Small Signal Transient Response for Various Feedback Capacitances
100 75
Figure 41. Large Signal Transient Response for Various Feedback Capacitances
1.5 RS = 111, CL = 5pF 1.0
50 RS = 111, CL = 5pF 25
0.5
VO, dm (V)
0 -25 -50
04771-0-039
VO, dm (V)
RS = 60.4, CL = 15pF 0
RS = 60.4, CL = 15pF
-0.5
-75 20ns/DIV -100 TIME (ns)
20ns/DIV -1.5 TIME (ns)
Figure 39. Small Signal Transient Response for Various Capacitive Loads
Figure 42. Large Signal Transient Response for Various Capacitive Loads
Rev. B | Page 13 of 24
04771-0-038
-1.0
04771-0-014
-1.0
04771-0-040
ERROR (V) 1DIV = 0.02%
AMPLITUDE (V)
AD8137
-5 PSRR = VO, dm/VS -15
1000
100
OUTPUT IMPEDANCE ()
-25 -35 -45 -55 -65 -75 -85 0.1
04771-0-011
PSRR (dB)
10
-PSRR +PSRR
1
0.1
04771-0-061
1
10 FREQUENCY (MHz)
100
0.01 0.01
0.1
1 10 FREQUENCY (MHz)
100
Figure 43. PSRR vs. Frequency
Figure 46. Single-Ended Output Impedance vs. Frequency
4.0
1 0 -1 -2
3.5 2V p-p 3.0
VO, cm (V)
CLOSED-LOOP GAIN (dB)
-3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 1 VO, dm = 0.1V p-p 10 100 FREQUENCY (MHz) VS = +3
04771-0-010
04771-0-050
1V p-p 2.5
VS = +5
VS = 5
2.0
1.5 20ns/DIV 1.0 TIME (ns)
1000
Figure 44. VOCM Small Signal Frequency Response for Various Supply Voltages
350
Figure 47. VOCM Large Signal Transient Response
SINGLE-ENDED OUTPUT SWING FROM RAIL (mV)
700 600 500
-300
345
-305 VON - VS-
300 200 100 0 -100 -200 -300 -400 -500 -600 -700 200 1k RESISTIVE LOAD () VON - VS-
04771-0-049
340
-310
VS = +5V
VS = +3V
335 VS+ - VOP
-315
330
-320
10k
320 -40
-330 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
Figure 45. Output Saturation Voltage vs. Output Load
Figure 48. Output Saturation Voltage vs. Temperature
Rev. B | Page 14 of 24
04771-0-065
325
-325
VON SWING FROM RAIL (mV)
VOP SWING FROM RAIL (mV)
400
VS+ - VOP
AD8137
0.3 15 2.60 0.2 10
VOS, cm
2.55
0.1
5
SUPPLY CURRENT (mA)
VOS, dm
2.50
VOS, dm (mV)
0
0
VOS, cm (mV)
2.45
-0.1
5
2.40
04771-0-052
-0.3 -40
-15 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
2.30 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 49. Offset Voltage vs. Temperature
1.2 1.0 70
Figure 52. Supply Current vs. Temperature
50
INPUT BIAS CURRENT (A)
0.8 0.6 0.4 0.2 0
04771-0-059
30
(A)
10
OCM
IV
-10
-30
04771-0-056
-0.2 -0.4 0.50
-50 -70 0 0.5 1.0 1.5 2.0 2.5 3.0 VOCM (V) 3.5 4.0 4.5
1.50
2.50 VACM (V)
3.50
4.50
5.0
Figure 50. Input Bias Current vs. Input Common-Mode Voltage, VACM
Figure 53. VOCM Bias Current vs. VOCM Input Voltage
0.40
3
-0.1
0.35
IBIAS
2 -0.2 1
VOCM CURRENT (A)
0.30
IBIAS (A)
0.25 IOS 0.20
IOS (nA)
0
-0.3
-1
-0.4
04771-0-053
04771-0-054
0.15
-2
0.10 -40
-3 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
-0.5 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 51. Input Bias and Offset Current vs. Temperature
Figure 54. VOCM Bias Current vs. Temperature
Rev. B | Page 15 of 24
04771-0-051
-0.2
10
2.35
AD8137
5 VS = +5V 4 3 2 1
VO, cm SUPPLY CURRENT (mA)
1.5 VS = 2.5V G = 1 (RF = RG = 1k) RL, dm = 1k INPUT = 1Vp-p @ 1MHz VO, dm 0.5
1.0
VS = +3V
0 -1 -2 -3 -4 -5 -5 -4 -3 -2 -1 0 VOCM 1 2 3 4 5
04771-0-060
0
VS = 5V
-0.5
PD -1.5
-2.0V
2s/DIV
TIME (s)
Figure 55. VO, cm vs. VOCM Input Voltage
40 20 0
PD CURRENT (A) SUPPLY CURRENT (mA)
Figure 58. Power-Down Transient Response
3.6 3.2 PD (0.8V TO 1.5V) 2.8 2.4 2.0 1.6 1.2 0.8
04771-0-057
-20 -40 -60 -80 -100 -120 0 0.5 1.0 1.5 2.0 2.5 3.0 PD VOLTAGE (V) 3.5 4.0 4.5
0.4 100ns/DIV 0 TIME (ns)
5.0
Figure 56. PD Current vs. PD Voltage
3.4
Figure 59. Power-Down Turn-On Time
3 IS + 2
SUPPLY CURRENT (mA) SUPPLY CURRENT (mA)
PD (1.5V TO 0.8V) 3.0 2.6 2.2 1.8 1.4 1.0 0.6 0.2 TIME (ns) 40ns/DIV
04771-0-025
1
0
-1
IS-
-3 0 0.5 1.0 1.5 2.0 2.5 3.0 PD VOLTAGE (V) 3.5 4.0 4.5
5.0
04771-0-058
-2
Figure 57. Supply Current vs. PD Voltage
Figure 60. Power-Down Turn-Off Time
Rev. B | Page 16 of 24
04771-0-024
04771-0-066
-1.0
-0.5V
AD8137 THEORY OF OPERATION
The AD8137 is a low power, low cost, fully differential voltage feedback amplifier that features a rail-to-rail output stage, common-mode circuitry with an internally derived commonmode reference voltage, and bias shutdown circuitry. The amplifier uses two feedback loops to separately control differential and common-mode feedback. The differential gain is set with external resistors as in a traditional amplifier while the output common-mode voltage is set by an internal feedback loop, controlled by an external VOCM input. This architecture makes it easy to arbitrarily set the output common-mode voltage level without affecting the differential gain of the amplifier.
100 80 60 40 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -180 -200 0.0001
04771-0-021
OPEN-LOOP GAIN (dB)
PHASE (DEGREES)
0.001
0.01 0.1 1 FREQUENCY (MHz)
10
100
Figure 62. Open-Loop Gain and Phase
VOCM ACM
-OUT
CP +IN CC
-IN CN CC
+OUT
Figure 61. Block Diagram
From Figure 61, the input transconductance stage is an H-bridge whose output current is mirrored to high impedance nodes CP and CN. The output section is traditional H-bridge driven circuitry with common emitter devices driving nodes +OUT and -OUT. The 3 dB point of the amplifier is defined as
In Figure 61, the common-mode feedback amplifier ACM samples the output common-mode voltage, and by negative feedback forces the output common-mode voltage to be equal to the voltage applied to the VOCM input. In other words, the feedback loop servos the output common-mode voltage to the voltage applied to the VOCM input. An internal bias generator sets the VOCM level to approximately midsupply; therefore, the output common-mode voltage will be set to approximately midsupply when the VOCM input is left floating. The source resistance of the internal bias generator is large and can be overridden easily by an external voltage supplied by a source with a relatively small output resistance. The VOCM input can be driven to within approximately 1 V of the supply rails while maintaining linear operation in the common-mode feedback loop. The common-mode feedback loop inside the AD8137 produces outputs that are highly balanced over a wide frequency range without the requirement of tightly matched external components, because it forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude and exactly 180 apart in phase.
gm BW = 2 x CC
where gm is the transconductance of the input stage and CC is the total capacitance on node CP/CN (capacitances CP and CN are well matched). For the AD8137, the input stage gm is ~1 mA/V and the capacitance CC is 3.5 pF, setting the crossover frequency of the amplifier at 41 MHz. This frequency generally establishes an amplifier's unity gain bandwidth, but with the AD8137, the closed-loop bandwidth depends upon the feedback resistor value as well (see Figure 19). The open-loop gain and phase simulations are shown in Figure 62.
04771-0-017
Rev. B | Page 17 of 24
AD8137 APPLICATIONS
ANALYZING A TYPICAL APPLICATION WITH MATCHED RF AND RG NETWORKS
Typical Connection and Definition of Terms
Figure 63 shows a typical connection for the AD8137, using matched external RF/RG networks. The differential input terminals of the AD8137, VAP and VAN, are used as summing junctions. An external reference voltage applied to the VOCM terminal sets the output common-mode voltage. The two output terminals, VOP and VON, move in opposite directions in a balanced fashion in response to an input signal.
CF
Output balance is measured by placing a well-matched resistor divider across the differential voltage outputs and comparing the signal at the divider's midpoint with the magnitude of the differential output. By this definition, output balance is equal to the magnitude of the change in output common-mode voltage divided by the magnitude of the change in output differentialmode voltage:
Output Balance =
VO , cm VO , dm
(3)
The differential negative feedback drives the voltages at the summing junctions VAN and VAP to be essentially equal to each other.
RF VIP VOCM VIN RG VAN RG VAP + VON - RL, dm VO, dm VOP RF
04771-0-055
VAN = VAP
(4)
AD8137
-
+
The common-mode feedback loop drives the output commonmode voltage, sampled at the midpoint of the two internal common-mode tap resistors in Figure 61, to equal the voltage set at the VOCM terminal. This ensures that
CF
Figure 63. Typical Connection
VOP = VOCM +
and (1)
VO , dm 2
(5)
The differential output voltage is defined as
VO, dm = VOP - VON
Common-mode voltage is the average of two voltages. The output common-mode voltage is defined as
VO , cm = VOP + VON 2
VON = VOCM -
VO , dm 2
(6)
ESTIMATING NOISE, GAIN, AND BANDWITH WITH MATCHED FEEDBACK NETWORKS
(2)
Estimating Output Noise Voltage and Bandwidth
The total output noise is the root-sum-squared total of several statistically independent sources. Since the sources are statistically independent, the contributions of each must be individually included in the root-sum-square calculation. Table 7 lists recommended resistor values and estimates of bandwidth and output differential voltage noise for various closed-loop gains. For most applications, 1% resistors are sufficient. Table 7. Recommended Values of Gain-Setting Resistors, and Voltage Gain for Various Closed-Loop Gains
Gain 1 2 5 10 RG () 1k 1k 1k 1k RF () 1k 2k 5k 10 k 3 dB Bandwidth (MHz) 72 40 12 6 Total Output Noise (nV/Hz) 18.6 28.9 60.1 112.0
Output Balance
Output balance is a measure of how well VOP and VON are matched in amplitude and how precisely they are 180 out of phase with each other. It is the internal common-mode feedback loop that forces the signal component of the output common-mode towards zero, resulting in the near perfectly balanced differential outputs of identical amplitude and exactly 180 out of phase. The output balance performance does not require tightly matched external components, nor does it require that the feedback factors of each loop be equal to each other. Low frequency output balance is ultimately limited by the mismatch of an on-chip voltage divider.
Rev. B | Page 18 of 24
AD8137
The differential output voltage noise contains contributions from the AD8137's input voltage noise and input current noise as well as those from the external feedback networks. The contribution from the input voltage noise spectral density is computed as
Feedback Factor Notation
When working with differential drivers, it is convenient to introduce the feedback factor , which is defined as RG RF + RG (14)
R Vo_n1 = vn 1 + F , or equivalently, vn/ RG
(7)
where vn is defined as the input-referred differential voltage noise. This equation is the same as that of traditional op amps. The contribution from the input current noise of each input is computed as
This notation is consistent with conventional feedback analysis and is very useful, particularly when the two feedback loops are not matched.
Input Common-Mode Voltage
The linear range of the VAN and VAP terminals extends to within approximately 1 V of either supply rail. Since VAN and VAP are essentially equal to each other, they are both equal to the amplifier's input common-mode voltage. Their range is indicated in the specifications tables as input common-mode range. The voltage at VAN and VAP for the connection diagram in Figure 63 can be expressed as VAN = VAP = VACM =
Vo_n 2 = in (RF )
(8)
where in is defined as the input noise current of one input. Each input needs to be treated separately since the two input currents are statistically independent processes. The contribution from each RG is computed as
R Vo_n 3 = 4 kTRG F RG
This result can be intuitively viewed as the thermal noise of each RG multiplied by the magnitude of the differential gain. The contribution from each RF is computed as Vo_n 4 = 4 kTRF
(9)
(V + VIN ) RG RF x IP x VOCM + 2 RF + RG RF + RG
where VACM is the common-mode voltage present at the amplifier input terminals. Using the notation, Equation (15) can be written as VACM = VOCM + (1 - )VICM
(15)
(16)
(10)
or equivalently, VACM = VICM + (VOCM - VICM ) (17)
Voltage Gain
The behavior of the node voltages of the single-ended-todifferential output topology can be deduced from the signal definitions and Figure 63. Referring to Figure 63, (CF = 0) and setting VIN = 0 one can write:
where VICM is the common-mode voltage of the input signal, that is
VICM VIP + VIN 2
VIP - VAP VAP - VON = RG RF
RG VAN = VAP = VOP RF + RG
(11) For proper operation, the voltages at VAN and VAP must stay within their respective linear ranges. (12)
Calculating Input Impedance
The input impedance of the circuit in Figure 63 depends on whether the amplifier is being driven by a single-ended or a differential signal source. For balanced differential input signals, the differential input impedance (RIN, dm) is simply
R IN, dm = 2 RG
Solving the above two equations and setting VIP to Vi gives the gain relationship for VO, dm/Vi.
VOP - VON = VO, dm = RF V RG i
(13)
(18)
An inverting configuration with the same gain magnitude can be implemented by simply applying the input signal to VIN and setting VIP = 0. For a balanced differential input, the gain from VIN, dm to VO, dm is also equal to RF/RG, where VIN, dm = VIP - VIN.
For a single-ended signal (for example, when VIN is grounded, and the input signal drives VIP), the input impedance becomes
R IN = RG RF 1- 2(RG + RF )
(19)
Rev. B | Page 19 of 24
AD8137
5V 0.1F 1k 1k VOCM +2.5V GND -2.5V VIN VREFB 3 8 2 1 + 5 50 1.0nF VDD VIN- 0.1F
AD8137
- 6 4 1k +1.88V +1.25V +0.63V 50
AD7450A
VIN+ 1.0nF GND VREF 2.5k ADR525A 2.5V SHUNT VREFA REFERENCE
1k
2.5V
VACM WITH VREFB = 0
Figure 64. AD8137 Driving AD7450A, 12-Bit A/D Converter
The input impedance of a conventional inverting op amp configuration is simply RG, but is higher in Equation 19 because a fraction of the differential output voltage appears at the summing junctions, VAN and VAP. This voltage partially bootstraps the voltage across the input resistor RG, leading to the increased input resistance.
5V
0.1F 3 8 2 1 +
1k 1k 5
VIN 0V TO 5V
VOCM
AD8137
- 6 4 1k 5V TO AD7450A VREF + 10k
Input Common-Mode Swing Considerations
In some single-ended-to-differential applications when using a single-supply voltage, attention must be paid to the swing of the input common-mode voltage, VACM. Consider the case in Figure 64, where VIN is 5 V p-p swinging about a baseline at ground and VREFB is connected to ground. The input signal to the AD8137 is originating from a source with a very low output resistance. The circuit has a differential gain of 1.0 and = 0.5. VICM has an amplitude of 2.5 V p-p and is swinging about ground. Using the results in Equation 16, the common-mode voltage at the AD8137's inputs, VACM, is a 1.25 V p-p signal swinging about a baseline of 1.25 V. The maximum negative excursion of VACM in this case is 0.63 V, which exceeds the lower input common-mode voltage limit. One way to avoid the input common-mode swing limitation is to bias VIN and VREF at midsupply. In this case, VIN is 5 V p-p swinging about a baseline at 2.5 V, and VREF is connected to a low-Z 2.5 V source. VICM now has an amplitude of 2.5 V p-p and is swinging about 2.5 V. Using the results in Equation 17, VACM is calculated to be equal to VICM because VOCM = VICM. Therefore, VICM swings from 1.25 V to 3.75 V, which is well within the input common-mode voltage limits of the AD8137. Another benefit seen by this example is that since VOCM = VACM = VICM, no wasted common-mode current flows. Figure 65 illustrates a way to provide the low-Z bias voltage. For situations that do not require a precise reference, a simple voltage divider will suffice to develop the input voltage to the buffer.
1k 0.1F 0.1F 10F +
04771-0-018
AD8031
-
0.1F
ADR525A 2.5V SHUNT REFERENCE
Figure 65. Low-Z Bias Source
Another way to avoid the input common-mode swing limitation is to use dual power supplies on the AD8137. In this case, the biasing circuitry is not required.
Bandwidth vs. Closed-Loop Gain
The AD8137's 3 dB bandwidth will decrease proportionally to increasing closed-loop gain in the same way as a traditional voltage feedback operational amplifier. For closed-loop gains greater than 4, the bandwidth obtained for a specific gain can be estimated as
f - 3dB ,VO, dm = RG x ( 72 MHz ) RG + RF
04771-0-019
(20)
or equivalently, (72 MHz). This estimate assumes a minimum 90 phase margin for the amplifier loop, a condition approached for gains greater than four. Lower gains will show more bandwidth than predicted by the equation due to the peaking produced by the lower phase margin.
Rev. B | Page 20 of 24
AD8137
Estimating DC Errors
Primary differential output offset errors in the AD8137 are due to three major components: the input offset voltage, the offset between the VAN and VAP input currents interacting with the feedback network resistances, and the offset produced by the dc voltage difference between the input and output common-mode voltages in conjunction with matching errors in the feedback network. The first output error component is calculated as
Driving a Capacitive Load
A purely capacitive load will react with the bondwire and pin inductance of the AD8137, resulting in high frequency ringing in the transient response and loss of phase margin. One way to minimize this effect is to place a small resistor in series with each output to buffer the load capacitance. The resistor and load capacitance will form a first-order, low-pass filter, so the resistor value should be as small as possible. In some cases, the ADCs require small series resistors to be added on their inputs. Figure 39 and Figure 42 illustrate transient response vs. capacitive load, and were generated using series resistors in each output and a differential capacitive load.
R + RG Vo_e1 = VIO F , or equivalently as VIO/ RG
where VIO is the input offset voltage. The second error is calculated as
(21)
Layout Considerations
Standard high speed PCB layout practices should be adhered to when designing with the AD8137. A solid ground plane is recommended and good wideband power supply decoupling networks should be placed as close as possible to the supply pins. To minimize stray capacitance at the summing nodes, the copper in all layers under all traces and pads that connect to the summing nodes should be removed. Small amounts of stray summing-node capacitance will cause peaking in the frequency response, and large amounts can cause instability. If some stray summing-node capacitance is unavoidable, its effects can be compensated for by placing small capacitors across the feedback resistors.
R + RG RG RF Vo_e 2 = I IO F = I IO (RF ) RG RF + RG
where IIO is defined as the offset between the two input bias currents. The third error voltage is calculated as Vo_e 3 = enr x (VICM - VOCM ) where enr is the fractional mismatch between the two feedback resistors.
(22)
(23)
The total differential offset error is the sum of these three error sources.
Terminating a Single-Ended Input
Controlled impedance interconnections are used in most high speed signal applications, and they require at least one line termination. In analog applications, a matched resistive termination is generally placed at the load end of the line. This section deals with how to properly terminate a single-ended input to the AD8137. The input resistance presented by the AD8137 input circuitry is seen in parallel with the termination resistor, and its loading effect must be taken into account. The Thevenin equivalent circuit of the driver, its source resistance, and the termination resistance must all be included in the calculation as well. An exact solution to the problem requires solution of several simultaneous algebraic equations and is beyond the scope of this data sheet. An iterative solution is also possible and is simpler, especially considering the fact that standard resistor values are generally used. Figure 66 shows the AD8137 in a unity-gain configuration, and with the following discussion, provides a good example of how to provide a proper termination in a 50 environment.
Additional Impact of Mismatches in the Feedback Networks
The internal common-mode feedback network will still force the output voltages to remain balanced, even when the RF/RG feedback networks are mismatched. The mismatch, however, will cause a gain error proportional to the feedback network mismatch. Ratio-matching errors in the external resistors will degrade the ability to reject common-mode signals at the VAN and VIN input terminals, similar to a four-resistor difference amplifier made from a conventional op amp. Ratio-matching errors will also produce a differential output component that is equal to the VOCM input voltage times the difference between the feedback factors (s). In most applications using 1% resistors, this component amounts to a differential dc offset at the output that is small enough to be ignored.
Rev. B | Page 21 of 24
AD8137
+5V
0.1F 1k 50 VIN 2V p-p RT 52.3 1k 0V VOCM 3 8 2 1 1.02k + 5 -
This example shows that when RF and RG are large compared to RT, the gain reduction produced by the increase in RG is essentially cancelled by the increase in the Thevenin voltage caused by RT being greater than the output resistance of the signal source. In general, as RF and RG become smaller in terminated applications, RF needs to be increased to compensate for the increase in RG. When generating the typical performance characteristics data, the measurements were calibrated to take the effects of the terminations on closed-loop gain into account.
04771-0-020
SIGNAL SOURCE
AD8137
- 6 + 1k 4
0.1F -5V
Power Down
The AD8137 features a PD pin that can be used to minimize the quiescent current consumed when the device is not being used. PD is asserted by applying a low logic level to Pin 7. The threshold between high and low logic levels is nominally 1.1 V above the negative supply rail. See the Specification tables (Table 1 to Table 3) for the threshold limits.
Figure 66. AD8137 with Terminated Input
The 52.3 termination resistor, RT, in parallel with the 1 k input resistance of the AD8137 circuit, yields an overall input resistance of 50 that is seen by the signal source. In order to have matched feedback loops, each loop must have the same RG if it has the same RF. In the input (upper) loop, RG is equal to the 1 k resistor in series with the (+) input plus the parallel combination of RT and the source resistance of 50 . In the upper loop, RG is therefore equal to 1.03 k. The closest standard value is 1.02 k and is used for RG in the lower loop. Things become more complicated when it comes to determining the feedback resistor values. The amplitude of the signal source generator VIN is two times the amplitude of its output signal when terminated in 50 . Therefore, a 2 V p-p terminated amplitude is produced by a 4 V p-p amplitude from VS. The Thevenin equivalent circuit of the signal source and RT must be used when calculating the closed-loop gain because RG in the upper loop is split between the 1 k resistor and the Thevenin resistance looking back toward the source. The Thevenin voltage of the signal source is greater than the signal source output voltage when terminated in 50 because RT must always be greater than 50 . In this case, RT is 52.3 and the Thevenin voltage and resistance are 2.04 V p-p and 25.6 , respectively. Now the upper input branch can be viewed as a 2.04 V p-p source in series with 1.03 k. Since this is to be a unity-gain application, a 2 V p-p differential output is required, and RF must therefore be 1.03 k x (2/2.04) = 1.01 k 1 k.
DRIVING AN ADC WITH GREATER THAN 12-BIT PERFORMANCE
Since the AD8137 is suitable for 12-bit systems, it is desirable to measure the performance of the amplifier in a system with greater than 12-bit linearity. In particular, the effective number of bits, ENOB, is most interesting. The AD7687, 16-bit, 250 KSPS ADC's performance makes it an ideal candidate for showcasing the 12-bit performance of the AD8137. For this application, the AD8137 is set in a gain of two and driven single-ended through a 20 kHz band-pass filter, while the output is taken differentially to the input of the AD7687 (see Figure 67). This circuit has mismatched RG impedances and, therefore, has a dc offset at the differential output. It is included as a test circuit to illustrate the performance of the AD8137. Actual application circuits should have matched feedback networks. For an AD7687 input range up to -1.82 dBFS, the AD8137 power supply is a single 5 V applied to VS+ with VS- tied to ground. To increase the AD7687 input range to -0.45 dBFS, the AD8137 supplies are increased to +6 V and -1 V. In both cases, the VOCM pin is biased with 2.5 V and the PD pin is left floating. All voltage supplies are decoupled with 0.1 F capacitors. Figure 68 and Figure 69 show the performance of the -1.82 dBFS setup and the -0.45 dBFS setup, respectively.
Rev. B | Page 22 of 24
AD8137
VS+ 20kHz GND 499 VIN BPF VOCM + 33 1.0k V+ VDD
AD8137
- 33 1.0k VS-
1nF
AD7687
GND
499 +2.5
1nF
04771-0-067
Figure 67. AD8137 Driving AD7687, 16-Bit 250 KSPS ADC
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 0 20 40 60 80 FREQUENCY (kHz) 0 -10
AMPLITUDE (dB OF FULL SCALE)
AMPLITUDE (dB OF FULL SCALE)
THD = -93.63dBc SNR = 91.10dB SINAD = 89.74dB ENOB = 14.6
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 0 20 40 60 80 FREQUENCY (kHz)
THD = -91.75dBc SNR = 91.35dB SINAD = 88.75dB ENOB = 14.4
04771-0-068
100
120
140
100
120
140
Figure 69. AD8137 Performance on +6 V, -1 V Supplies, -0.45 dBFS
Figure 68. AD8137 Performance on Single 5 V Supply, -1.82 dBFS
Rev. B | Page 23 of 24
04771-0-069
AD8137 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 70. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
3.00 BSC SQ 0.60 MAX 0.50 0.40 0.30 PIN 1 INDICATOR
8
1
PIN 1 INDICATOR
TOP VIEW
2.75 BSC SQ 0.50 BSC
5
EXPOSED PAD
(BOTTOM VIEW)
1.50 REF
4
1.89 1.74 1.59
0.90 MAX 0.85 NOM
12 MAX
0.70 MAX 0.65 TYP 0.05 MAX 0.01 NOM
1.60 1.45 1.30
SEATING PLANE
0.30 0.23 0.18
0.20 REF
Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm x 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8137YR AD8137YR-REEL AD8137YR-REEL7 AD8137YRZ1 AD8137YRZ-REEL1 AD8137YRZ-REEL71 AD8137YCP-R2 AD8137YCP-REEL AD8137YCP-REEL7 AD8137YCPZ-R21 AD8137YCPZ-REEL1 AD8137YCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Standard Small Outline Package (SOIC_N) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD) 8-Lead Lead Frame Chip Scale Package (LFCSP_VD)
Package Option R-8 R-8 R-8 R-8 R-8 R-8 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2 CP-8-2
Branding
HFB HFB HFB HFB# HFB# HFB#
Z = Pb-free part; # denotes lead-free, may be top or bottom marked.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04771-0-7/05(B)
Rev. B | Page 24 of 24

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